-
- News
- Books
Featured Books
- design007 Magazine
Latest Issues
Current IssueLevel Up Your Design Skills
This month, our contributors discuss the PCB design classes available at IPC APEX EXPO 2024. As they explain, these courses cover everything from the basics of design through avoiding over-constraining high-speed boards, and so much more!
Opportunities and Challenges
In this issue, our expert contributors discuss the many opportunities and challenges in the PCB design community, and what can be done to grow the numbers of PCB designers—and design instructors.
Embedded Design Techniques
Our expert contributors provide the knowledge this month that designers need to be aware of to make intelligent, educated decisions about embedded design. Many design and manufacturing hurdles can trip up designers who are new to this technology.
- Articles
- Columns
Search Console
- Links
- Events
||| MENU - design007 Magazine
IPC Design Competition Champion Crowned at IPC APEX EXPO 2024
April 24, 2024 | IPCEstimated reading time: 1 minute
At IPC APEX EXPO 2024 in Anaheim, California, five competitors squared off to determine who was the best of the best at PCB design.
As finalists in the third annual IPC Design Competition, the five designers were invited to IPC APEX EXPO to compete in a five-hour layout challenge, to place components and route a board, compliant to relevant IPC standards. As part of the finals heat, competitors used Altium Designer, and a project was provided with stackup and board geometry complete, with certain critical components pre-placed. All other components were left to be placed at the discretion of the competitors.
At the end of the round, each competitor delivered their project file to judges Kris Moyer and Patrick Crawford, IPC; Steve Roy, Roy Design and Manufacturing Service; Russell Steiner, Amphenol; Kevin Kusiak and David Caputa, Lockheed Martin. The judges placed weight on examining completeness of the board (i.e., how many routed nets) vs. critical errors – namely short circuits, clearance violations, via producibility, and various signal integrity aspects.
After an intense 2.5-hour judging process, Dinesh G., lead turnkey, Sienna ECAD, took first place with his PCB design.
Second place went to Paul Brionez, CID+, senior PCB design layout engineer, Wisk Aero. Third place went to Ajeesh Francis, senior PCB engineer, Tessolve Semiconductor Pvt. Ltd.
Runners-up included: Joseph Chiu, ToyBuilder Labs and Harish G., senior engineer, R&D-Mobility, Exicom Tele-Systems Ltd.
To learn more about IPC’s design initiative, visit ipc.org/solutions/ipc-design.
Suggested Items
Indium Corporation to Showcase HIA Materials at ECTC
05/07/2024 | Indium CorporationAs an industry leader in innovative materials solutions for semiconductor packaging and assembly, Indium Corporation® will feature its advanced products designed to meet the evolving challenges of heterogeneous integration and assembly (HIA) and fine-pitch system-in-package (SiP) applications at the 74th Electronic Components and Technology Conference (ECTC), May 28‒31, in Denver, Colorado.
Siemens Delivers New Solido IP Validation Suite
05/07/2024 | SiemensSiemens Digital Industries Software introduced Solido™ IP Validation Suite software, a comprehensive, automated signoff solution for quality assurance across all design intellectual property (IP) types, including standard cells, memories and IP blocks.
Altair Acquires Research in Flight, Forging a New Path for Aerodynamic Analysis
05/07/2024 | AltairAltair a global leader in computational intelligence, announced it has acquired Research in Flight, maker of FlightStream®, which provides computational fluid dynamics (CFD) software with a large footprint in the aerospace and defense sector and a growing presence in marine, energy, turbomachinery, and automotive applications.
Happy’s Tech Talk #28: The Power Mesh Architecture for PCBs
05/07/2024 | Happy Holden -- Column: Happy’s Tech TalkA significant decrease in HDI substrate production cost can be achieved by reducing the number of substrate layers from conventional through-hole multilayers and microvia multilayers of eight, 10, 12 (and more), down to four. Besides reducing direct processing steps, yield will increase as defect producing operations are eliminated.
Hirose Launches Solution Partner Network to Address Changing Design Challenges
05/06/2024 | HiroseHirose, a leader in the design and manufacturing of innovative connector solutions, has established a Solution Partner Network that enables OEMs to quickly explore product design, specialty IP, and component fulfillment options that best suit their needs.